Front End Design Methodology and Verification Engineer

Grow With US:

Infrastructure Front-End CAD Engineer (ASIC/FPGA) at Ericsson Silicon in Austin, Texas.

This is not a remote position opportunity

Are you interested in shaping the future of Ericsson Silicon's Verification methodology and tools? Join our dynamic team within the newly established Frontend CAD department, dedicated to defining methodologies and EDA workflows across our global R&D sites located in Austin, Stockholm, and Lund.

About Us:

The Team is part of the Ericsson Silicon engineering unit, which develops state of the art ASIC's and FPGA's targeting the newest technology nodes for Ericsson's 5G telecommunication product portfolio. This department offers many opportunities for career growth and a large base of knowledge to learn from.

What You Will Do:

To excel in this high-visibility role, we seek individuals with a background in ASIC IP/ASIC SOC development, a profound interest in system-on-chip design & verification and a deep interest in methodologies and tools increasing efficiency of our global engineering community.

As a key member within the Frontend CAD (FE CAD) department, you will play a crucial role in shaping and optimizing methodologies and EDA workflows, ensuring seamless adoption of industry best practices for crafting efficient System on Chips (SoCs).

The ideal candidate is driven by solving new technical challenges, good at identifying areas for improvement in methodologies, tools, and support structures, have a keen interest in learning new skills, and are dedicated to continuous improvement, you might be the perfect fit for us, contribute to our dynamic team and shape the future of our silicon design endeavors.

What you will bring:

Hands on experience in ASIC IP/ASIC SoC design, RTL, Verilog, UVM, and System Verilog.
Exposure to front-end tools including Verilog simulators, RTL/Verification linters, clock domain crossing checkers.
Familiarity with synthesis, static timing analysis, Design-For-Test (DFT).
Knowledge of System-Verilog assertions, checkers, and advanced design verification techniques ais advantageous.
Familiarity with CloudBees Jenkins continuous integration methodologies.
Proficiency in scripting languages such as Perl, Python, bash, csh, etc.
Some understanding of modern design methodologies and techniques.
Exposure to compute batching solutions such as LSF (Load Sharing Facility), Slurm, and Altair.
Effective communication and presentation skills.
Responsibilities:

Involved in the day-to-day development, deployment, and support of complex tool flows in Frontend Design & Verification.
Involved in innovation in design processes and methodologies.
Foster Cross-functional Collaboration by working closely with different teams such as design, verification, testing, and manufacturing.
Facilitate effective communication and collaboration among these groups.
Troubleshooting Skills: Identify and address technical challenges that arise during the silicon design process.
Demonstrate strong critical thinking skills to identify and address technical challenges during the silicon design process.
Implement processes for ensuring the quality of silicon design, including rigorous design reviews, testing methodologies, and quality assurance practices.
Foster a collaborative and positive work environment.

Education & Experience

BS/MS, Electrical Engineering, Computer Science or similar with several years of hands on, in industry experience.

Base Pay Range: $139,000 to $208,400