New

Recent Graduate-Process Engineer - Advanced Semiconductor Packaging

Keysight Technologies
paid holidays, tuition reimbursement, flex time, 401(k)
United States, California, Santa Rosa
1400 Fountaingrove Parkway (Show on map)
Nov 04, 2026
Overview Overview Keysightis at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn moreabout what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions.We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. We provide semiconductor technologies that drive Keysight's market leadership and revenue. The High Frequency Technology Center (HFTC) is seeking a Process Engineer in Advanced Packaging to develop next generation technologies and new products. Experience in microelectronics assembly, die attach, surface mount technology (SMT) or other relevant hands-on experience is required for success. This position is onsite at Keysight Headquarters in Santa Rosa, CA. Live in beautiful Sonoma County amongst vineyards, redwood forests, rivers, lakes and coastline while working on state-of-the-art advanced packaging technologies. HFTC is a world-class semiconductor organization that invents, designs, and manufactures state-of-the-art custom integrated circuits (ICs) to enable the industry's highest-performance test and measurement solutions. HFTC's proprietary indium phosphide (InP) and gallium arsenide (GaAs) semiconductor, silicon and heterogeneous integration technologies make possible some of the world's highest-speed and highest-frequency Monolithic Microwave Integrated Circuits (MMICs) and System in Package (SiP) products. Our chips and systems are custom designed to enable instrumentation with unmatched signal fidelity, bandwidth, and dynamic range. Keysight's 50,000 sq. ft. microfabrication facility-paired with deep expertise in design, modeling, and advanced compound semiconductor and silicon manufacturing-provides a distinct competitive advantage in delivering industry-leading performance. Responsibilities We focus on process research and development, process integration, and New Product Introduction.You will lead the development of next-generation System in Package (SiP) modules that will be integrated with microwave and mmWave subsystems across Keysight, serving multiple industries. Drive process control and stability through statistical process control (SPC), root cause analysis, and corrective actions using statistical tools (e.g., JMP) Work closely with other process, integration, product, and SiP design engineers to define process and performance targets Defining process flows, develop new processes and drive continuous process improvement (CPI) efforts to maximize product yield Develop and maintain high yields; report process metrics, root cause investigations, and process change implementations at the department level Ensure successful process hand off to manufacturing partners Work with Operations to implement robust process control and support production processes; diagnose and resolve process problems with urgency Champion and lead capital equipment acquisition projects that include tool evaluation, characterization, process development, and qualification Propose Desing of Experiment (DOE) plans, conducting experiments, and implementing process changes in a controlled fashion. Collaborate with equipment engineering on tool performance optimization, preventive maintenance strategies, throughput enhancements Lead technical development of new SiP introductions in collaboration with upstream design teams, process and manufacturing teams, and downstream customer teams Meet accelerated project schedules; communicate and manage risks Develop and maintain high yields while adhering to project schedules Depending on the candidate's expertise, responsibilities may include one or more of the following domains: Die attach: flip chip and thermocompression bonding (TCB) Surface cleaning and preparation Automatic adhesive dispense and pick and place, SMT Automatic die singulation and sort Metrology: profilometry, SEM, XRF, optical microscopy, automatic inspection Broader experience in upstream and downstream processes and the ability to understand process interactions is valued. Review new designs for manufacturability and provide feedback to module designers Qualifications Required Qualifications M.S. or Ph.D. in Materials Science, Physics, Chemistry, Mechanical Engineering, Manufacturing Engineering, Mechatronics, or relevant fields coupled with applicable experience training and interest in semiconductor fabrication processes. B.S. graduates with relevant experimental research experience will also be considered. Qualified candidates must be a recent graduate in 2026 or degree completed by June 2027. Candidates must be local or willing to relocate to Santa Rosa, CA We are seeking a recent graduate with expertise/academic training or internship experience in one or more of the following areas: Cleanroom, microelectronics, or related experimental research Proven experience in process development and data-driven process optimization Strong problem-solving and analytical skills for controlling process variation Excellent interpersonal, verbal, written and presentation communication skills. The successful candidate must be able to communicate complex technical information in a clear, concise, and direct manner, present data effectively to both small and large audiences, and collaborate productively across cross-functional teams. Strong accountability, self-initiative and proactive attitude are required for success. The following qualifications are desired but not required: Industrial semiconductor, advanced packaging, or Heterogeneous integration experience Familiarity with programming and operating automatic assembly equipment Knowledge of and experience with forming metallurgical bonds between similar metals Experience with adhesives, underfill materials, and dispense processes Experience with wafer singulation processes Thermal, mechanical and electrical reliability Project lifecycle III-V compound semiconductors and/or silicon technologies Candidates must be local or willing to relocate to Santa Rosa, CA This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items.Candidates must be a U.S. citizen or lawful permanent resident of the U.S., or protected individual, having authorization from the U.S. government for export-controlled items under 8 U.S.C. 1324b(a)(3). Keysight is an Equal Opportunity Employer. Careers Privacy Statement The level of role will be based on applicable experience, education and skills; Most offers will be between the minimum and the midpoint of the Salary Range listed below. Santa Rosa, CA Pay Range: MIN $76,870.00 - MAX $191,030 Note: For other locations, pay ranges will vary by region. This role is eligible for Keysight Results Bonus Program and US Employees may be eligible for the following benefits: Medical, dental and vision Health Savings Account Health Care and Dependent Care Flexible Spending Accounts Life, Accident, Disability insurance Business Travel Accident and Business Travel Health 401(k) Plan Flexible Time Off, Paid Holidays Paid Family Leave Discounts, Perks Tuition Reimbursement Adoption Assistance ESPP (Employee Stock Purchase Plan) #LI-MED1