Senior SoC Power Architect

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• Own the definition/refinement of power management feature setsand algorithmic behaviors (low power modes, performance states, transitions/state tables) in partnership with PMFW/FW/BIOS and platform stakeholders.
• Drive clear articulation of use cases power behavior requirements, including guardbands/constraints that impact targets and bounding box decisions.
• Lead technical reviews for power management architecture readiness and track feature closures across teams (arch FW/BIOS validation).

• Own rail-level power/current requirement definitionacross representative operating points and key workloads; provide actionable requirements to platform/package and drive rail tradeoffs and consolidation proposals with senior power architects.
• Produce and maintain program collateral: rail maps, power/current profiles, and "what changes what" analysis for platform readiness discussions.

• Lead PI execution for assigned critical rails and interfaces, including mission mode and state transitions, ensuring modeling readiness, closure of blockers, and a clear mitigation path (decaps, ondie regulation, input rail choices, etc.).
• Drive the PI handshake across stakeholders (SIPI/packaging/platform/PHY teams), ensuring requirements and inputs are in place and outcomes are tracked to closure.

• Drive power targets and bounding box (BBox)readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).
• Own a structured "open items" closure mechanism for power topics (risks, dependencies, decisions needed) and represent the workstream in crossfunctional program forums.

• Partner closely with the power modeling teamto align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.
• Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.

• Strong understanding of SoC power architecture fundamentals: rails, low power modes, performance states, and power targets/use cases.
• Working knowledge of PDN and PIprinciples (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
• Demonstrated ability to lead complex crossfunctional execution (architecture FW/BIOS validation package/platform).
• Experience leading PI/PDN analysis closure across rails/interfaces and translating results into architecture/platform requirements.
• Familiarity collaborating with presilicon power modeling teams and aligning architecture assumptions/targets with projections.
• Experience with program milestone readiness (bringing a technical workstream to a "reviewready" state).

• BS/MS in EE/CE (or equivalent) with expert levelof relevant experience (leveling flexible based on depth).

Location: Austin, TX

This role is not eligible for visa sponsorship.

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

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This posting is for an existing vacancy.